1. Field of the Invention
The present invention relates to a method for designing multi-threshold complementary metal-oxide-semiconductor (MTCMOS) circuits and the physical architecture of the circuits resulting from using such a method. In particular, the present invention relates to a design method to allow flexible simulation and verification of an MTCMOS circuit.
2. Discussion of the Related Art
A significant concern in integrated circuit design is reducing leakage currents. Leakage currents flow in logic circuits from a power supply node into the ground node because the switching characteristics of the transistors in the logic circuits are not ideal (i.e., the transistors cannot be completely shut off).
In MTCMOS circuits, one technique that reduces leakage current is to a place a “power gate” (also known as “power switch” or simply, “switch cell”) between the lowest potential terminal of a logic gate (the “virtual ground” reference) and the ground reference. This technique is illustrated schematically in FIG. 1, which shows power gate or switch cell 101 controlling the leakage current path of logic cell 102 to ground. As shown in FIG. 1, logic cell 102 is formed using lower threshold voltage transistors to provide short switching times. The power gate is typically a transistor which has a higher threshold voltage than the threshold voltage of the transistors used to implement the logic cells. The power gate interrupts the leakage current path to ground. When power gate 101 is conducting (i.e., a high voltage is provided at control node 106), a leakage current flows from power supply node 104 through logic cell 102 to virtual ground node 103, and through power gate 101 to true ground node 105. However, during standby (i.e., when a voltage much less than power gate 101's threshold voltage is imposed at control node 106), power gate 101 cuts off the leakage current path from virtual ground node 103 to true ground node 105.
Important concerns that are addressed by a designer of an MTCMOS circuit include:                1. Each logic cell is designed such that power-gating has minimal or little impact on the area and performance characteristics of the logic cell;        2. The logic and switch cells, wires, and connectors are laid out in an area-efficient manner;        3. The functional and timing behaviors of a logic cell are modeled with consideration for the anticipated effects of power gate switching on the logic cell;        4. The timing characteristics of the MTCMOS circuit takes into account the timing paths involving the virtual ground or power signals.        5. The functional behavior of the MTCMOS circuit are simulated with the effects of the virtual ground or virtual power signals;        6. The circuit after power-gates are synthesized and inserted may be verified to be functionally identical to that circuit prior to power gate synthesis;        7. A physical floor plan can be created with consideration for the virtual ground or virtual power networks;        8. The logic cells and switch cells that are connected by the same virtual ground or virtual power signals are placed effectively;        9. Virtual ground networks are effectively routed with the routing of all power, ground, and signal wires;        10. The amount of additional area required by including the virtual ground network or virtual power network are controlled.        11. The overall amount of time required to design and verify the logic, electrical and physical designs, including the design of the virtual ground or the virtual power network, can be minimized.        
Conventional design automation techniques treat a virtual ground network or a virtual power network in an MTCMOS circuit as a third power or ground network, in addition to the conventional power and ground networks, so that the functional and timing characteristics related to the switching of such “virtual ground” and “virtual power” reference signals and their impact on the functional and timing characteristics of the rest of the MTCMOS circuit are not modeled.